library verilog;
use verilog.vl_types.all;
entity lab6 is
    port(
        overflow        : out    vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        cin             : in     vl_logic;
        wr              : in     vl_logic;
        rd              : in     vl_logic;
        is_write        : in     vl_logic;
        btn             : in     vl_logic_vector(1 downto 0);
        key_row         : in     vl_logic_vector(3 downto 0);
        key_sel         : in     vl_logic_vector(1 downto 0);
        m               : in     vl_logic_vector(1 downto 0);
        ra              : in     vl_logic_vector(1 downto 0);
        remain          : in     vl_logic_vector(3 downto 0);
        key_col         : out    vl_logic_vector(3 downto 0);
        seg             : out    vl_logic_vector(7 downto 0);
        sel             : out    vl_logic_vector(2 downto 0)
    );
end lab6;
